The present disclosure relates to semiconductor memory devices, such as static random access memories (SRAMs) and the like, and more particularly to techniques of controlling voltages of bit lines.
In recent years, as semiconductor microfabrication technologies have been advanced to reduce the sizes of miniature structures, the reliability (resistance to electrical stress, thermal stress, and the like) of semiconductor elements have been degraded.
In general semiconductor memory devices, such as SRAMs, data is written to a memory cell by the potential of one of a pair of bit lines which have been precharged high transitioning from high to low.
For example, Japanese Patent Publication No. 2002-298586 describes a technique of improving a characteristic of write operation to a memory cell at a low power supply voltage by causing the potential of a bit line during data write operation to the memory cell to be smaller than 0 V.